This invention relates generally to logging mechanisms. The invention is more specifically related to a logging mechanism for ASIC simulations and other data intensive and/or multi platform logging devices.
Electronic design automation (xe2x80x9cEDAxe2x80x9d) is becoming increasingly complicated and time consuming, due in part to the greatly increasing size and complexity of the electronic devices designed by EDA tools. EDA tools include verification systems for general purpose microprocessors as well as custom logic devices including Application Specific Integrated Circuits (xe2x80x9cASICsxe2x80x9d) Examples of ASICs include non-programmable gate arrays, field programmable gate arrays (xe2x80x9cFPGAsxe2x80x9d), and complex programmable logic devices (xe2x80x9cPLDsxe2x80x9dor xe2x80x9cCPLDsxe2x80x9d). The design of even the simplest of these devices typically involves generation of a high level design, logic simulation, generation of a network, timing simulation, etc.
An ASIC verification system enables concurrent simulation of related hardware components (including ASIC under test, simulator of host computer, simulator of network media module and other peripherals). Simulation activity needs to be recorded, and, at least in early simulations, generally, each single activity of simulation needs to be tagged. Activity tagging can be either cycle-based or function-based. By convention, we call all this information on simulation activity, log information. Since cycle-based recording is generally supported by the CAD tools of conventional vendors, it is not included in this discussion. The discussion here focuses on the management of log information that is function-based tagged. Function-based tagged information makes understanding of the simulation more intuitive. This same intuitive understanding is not easily achieved when using cycle-based log information.
Generally, log information is reported and recorded throughout the simulation. Monitoring and recording simulation flow at a functional level plays a vital role in tracing and debugging, although there are a pair of factors that determines the efficiency and cost of a log information mechanism in a verification system.
One of the factors is the granularity of log information, i.e. the frequency of reporting and recording log information. Granularity affects the efficiency of log information mechanism, since the more detail the log information is, the more informative it is. On the other hand, simulation speeds are inversely proportional to the increasing granularity of the log information. Function-based log information can help to locate the occurrence of a bug.
Another factor is disk space and how to properly control the disk volume consumed by recording log information. Disk consumption of a log is especially large in a pseudo random and iterative verification systems, where the system is designed to exhaust the simulation variations by pseudo random or iterative generation of simulation stimuli. For a verification system of medium complexity, the size of a log file for a single component in the verification system can easily reach multi-gigabytes or more.
The most common approach to saving log information is to save the information to a single file. Verification. engineers then search that large file to find verification, error, or other information needed for specific tests or verification. However, when the amount of error (or other data) checking and reporting performed by the system becomes large, the tasks of creating and searching the file are either inefficient in that they are time consuming or cumbersome.
The present inventors have realized that automated checking and error reporting in an ASIC verification environment generates a detailed but cumbersome log of a simulation performed for the verification, and that the log information related to a particular problem may be contained across multiple modules. The present invention reduces the amount of information in a log by reporting messages related to an error or other trigger event in a window of simulation time near the error or other trigger. The size of the window is programmable depending on the nature of the error, the trigger, or other factors.
In addition, the present invention provides a better logical view of the log information. A synchronized disk save is performed on virtual windows from the various modules that perform the verification operations. Log information from the various windows is saved in the log file in relation to the time that the information is retrieved.
The present inventors have also realized that disk I/O operations in the logging process are time consuming and are slowing progress of the simulation and verification process. The present invention provides a circular memory buffer in which log information is stored. A window of the logged information is maintained in the circular buffer and saved to disk when a trigger is generated (error, for example).
The present invention eliminates side effects of fine granularity associated with log information, freeing verification engineers to collect log information with a necessary level of information. The invention also reduces disk I/O operations to improve speed of testing and regression testing. And, the present invention provides a better logical view of log information by centralizing the log information in a dynamically controlled virtual window.
The present invention may be embodied as a method of collecting log information for a Device Under Test (DUT), comprising the steps of, setting up an environment of operating conditions for the. DUT, applying at least one test stimuli to the DUT, collecting log information from the DUT that results from said environment and the applied test stimuli, and saving the log information in a log information file. The data may be collected from multiple modules, and the saving of log information from the multiple modules is performed synchronously.
The method may be conveniently implemented on a general purpose computer, or networked computers, and the results may be displayed on an output device connected to any of the general purpose, networked computers, or transmitted to a remote device for output or display. The present inventors have determined that, using the techniques described herein, in an ASIC verification environment, at the RTL level, that 80% of the disk space used in conventional verification systems can be saved while still providing enough log information to do adequate diagnosis and error tracking. Disk space savings are higher at the netlist level of verification.